1. Field of the Invention
This invention relates generally to the analysis of electronic signals, and, more particularly, to the analysis of the frequency content of electronic signals using parallel analog-to-digital converters.
2. Description of Related Art
A need commonly arises in electronic applications for analyzing the frequency content of electronic signals. One of these applications is automatic test equipment, or ATE. ATE systems, or “testers,” are generally complex electronic systems for verifying the operation of electronic devices or assemblies.
FIG. 1 is a high level block diagram of a tester. A host computer 110 runs a test program developed for testing a unit under test, or UUT 118. The host computer 110 interactively communicates with a clock distribution circuit 112 and source/capture instruments 114. These instruments provide stimuli to and monitor responses from the UUT 118 via an interconnect 116. Examples of testers are well known in the art, and include the Catalyst™, Tiger™, and Panther™ test systems designed by Teradyne, Inc. of North Reading, Mass.
In ATE as well as other applications, frequency analysis of electronic signals is generally conducted using a combination of measurement and computation. Conventionally, electronic signals are digitized by a device called an analog-to-digital converter, or “ADC.” The ADC is induced to acquire discrete samples of an analog signal at regular intervals of time. The samples emerge from the ADC as numeric codes, for which each code represents the level of the analog signal at the instant the respective sample is taken. The codes are then mathematically manipulated, using an algorithm called a discrete Fourier transform, or DFT, to produce the desire power spectrum. The power spectrum gives information about the amplitude and phase of frequency components that make up the original analog signal.
As is known, a limitation of this technique is that the digital output of the ADC can only unambiguously represent the analog input signal over a certain maximum bandwidth. This bandwidth is known as the “Nyquist bandwidth,” and equals FS/2, where FS is the sampling frequency. The first interval of the Nyquist bandwidth, or “Nyquist band,” starts at DC and ends at FS/2. The frequency FS/2 is sometimes referred to as the “Nyquist rate.”
If the analog signal has a bandwidth greater than the Nyquist bandwidth, frequency components falling outside the Nyquist bandwidth are manifested as errors in the sampled data, known as aliasing. Aliasing can be avoided by ensuring that the analog signal is band limited (e.g., filtered), so that its frequency content is contained within one Nyquist band. Generally, this means low pass filtering the analog signal so that it is rolled off at or before the Nyquist rate.
For analyzing signals having greater bandwidths, designers have sought to develop faster ADCs. Faster ADCs allow FS, and therefore the Nyquist bandwidth, to be increased. As is known, however, faster ADCs tend to be more costly than conventional designs. They also tend to sacrifice accuracy in exchange for speed.
Another approach is to use multiple, interleaved ADCs connected in parallel. One example of this approach is shown in FIG. 1. There, M different ADCs 110a-110m each have an input connected to an input node, Analog In. Each ADC also has an output connected to a selector 114. The ADCs each receive a clock signal (C1-CM), which induces them to convert their respective analog input signals to digital output signals. The clock signals are generally produced by the clock distribution circuit 112 of the ATE system. Each of the clock signals has a frequency FS, and each is delayed with respect to its predecessor. Intervals between successive clock signals are preferably identical and have a value equal to 1/(MFS). This arrangement ensures that the analog input signal is sampled uniformly at a rate MFS, while each ADC operates at a rate of only FS.
The digital output signals from the ADCs 110a-m are interleaved to create a stream of digital values (Digital Out) that honorably represents the analog input signal as a function of time. A common method of interleaving is shown. A selector 114 has M inputs that receive the digital output signals from the ADCs. The selector 114 also has a control input connected to a counter 116. The counter is clocked at a frequency MFS, and is made to cyclically count between 0 and M-1. For each count of the counter 116, the selector 114 selects a different one of its inputs for conveyance to its output. In this manner, the selector 114 assembles Digital Out from the values of the ADCs, in the right order. A capture memory 218 receives and stores values of Digital Out, and a processor 120 acts upon the stored values for computing power spectra or for otherwise analyzing or processing the signal.
Since the interleaved topology of FIG. 1 has an effective sampling rate of MFS, it has an effective Nyquist bandwidth of MFS/2 and represents a factor of M improvement over the single converter topology.
The interleaved topology of FIG. 1 offers great benefits, but they come at a cost. Just as speed is increased by a factor of M, so is cost and complexity.
What is needed is a less complex and less costly approach to analyzing the frequency content of high speed analog signals.